Very large scale integrated (VLSI) circuits are tested using automatic test equipment ("ATE") that typically test whether the VLSI circuit or device under test ("DUT") is fully functional according to a "stuck-at fault" testing model. Such functional testing requires the application of a set of input "test vectors" to the DUT to determine if the DUT provides the expected output for each test vector. Each test vector is a combination of input signals that causes the logic of the DUT to change states. Whether the logic of the DUT changes states can be determined by monitoring the outputs of the DUT.
Wherein functional testing is adequate for detecting many types of device defects, there are several types of defects that functional testing may not detect effectively. These defects include (1) gate oxide shorts, (2) bridging defects, (3) punchthrough, (4) parasitic transistor leakage, (5) leaky p-n junctions, (6) open drain or source defects, (7) open gate defects, and (8) transmission gate opens. Devices having such defects may pass standard functional testing, but they will ultimately have a shorter life span than devices without such defects.
For CMOS circuits, it has been discovered that testing the quiescent power supply current I.sub.DDQ of the DUT may increase the rate of detection for the above-mentioned defects. It has also been discovered that testing the I.sub.DDQ of the DUT is useful for the detection of design and fabrication errors. The quiescent power supply current I.sub.DDQ of a CMOS DUT is theoretically equal to zero when the logic of the DUT is in any known state.
FIG. 1A shows a DUT 100 configured for testing by an ATE (not shown). The DUT 100 includes a plurality of input conductors to which the ATE is coupled for providing input test vectors to the DUT 100. The DUT 100 also includes a plurality of output conductors which are coupled to the ATE for providing output signals to the ATE in response to the input signals provided by the ATE. Thus, the ATE can determine whether the logic of DUT 100 correctly changes states.
The DUT 100 may be, for example, a CMOS VLSI circuit comprising many thousands of CMOS inverters, the fundamental building block of CMOS circuits. One such CMOS inverter is shown as including an NMOS field effect transistor ("FET") Q1 and a PMOS FET Q2. The gates of FET Q1 and FET Q2 are coupled together for receiving the same input signal. The input signal may be provided directly by an input conductor of the DUT 100 or by the output of another CMOS inverter. The drain of FET Q2 is coupled to receive a power supply voltage V.sub.DD from a power supply, and the source of the FET Q2 is coupled to the drain of FET Q1. The source of FET Q1 is coupled to system ground, VSS. The output of the CMOS inverter is taken from the node shared by the source of FET Q2 an the drain of FET Q1.
The quiescent power supply current I.sub.DDQ of a CMOS inverter is ideally equal to zero because, theoretically, only one of the FETs Q1 and Q2 is switched on at any given time. Thus, no conduction path is provided between the power supply and ground. If the input signal is a logic low, FET Q2 is switched on and FET Q1 is switched off, which causes the output of the CMOS inverter to be tied to V.sub.DD, pulling the output up to a logic high level. Conversely, if the input signal is logic high, FET Q1 is switched on and FET Q2 is switched off, which causes the output of the CMOS inverter to be tied to VSS, pulling the output down to a logic low level. This behavior is shown in FIG. 1B. Curve 105 shows the input signal VIN, and curve 110 shows the output signal VOUT.
Practically speaking, however, the quiescent power supply current I.sub.DDQ of a typical CMOS inverter is some nominal, non-zero value. This is because neither of the FETs Q1 and Q2 are typically ever switched completely off, and a small conduction path is provided. A typical I.sub.DDQ value for a non-defective CMOS is less than 20 nA.
Defective CMOS VLSI circuits can exhibit elevated I.sub.DDQ levels in response to the appropriate test vectors. The defects listed above typically lead to conduction paths and therefore result in an elevation of the quiescent power supply current I.sub.DDQ that is greater than the I.sub.DDQ of a non-defective CMOS device. Thus, monitoring the I.sub.DDQ of a CMOS VLSI circuit can result in the detection of defects that are unlikely to be detected using standard functional testing.
FIG. 1C shows the behavior of the power supply current I.sub.DD over time. Before time t0, the CMOS inverter is in a known state, and the quiescent power supply current I.sub.DDQ is nominal value, as shown by arrow 115. At time t0, the CMOS inverter changes states, resulting in a current transient shown by arrow 120. This current transient is expected as both of the FETs Q1 and Q2 are conducting when switching between states. If the CMOS inverter is not defective, the power supply current I.sub.DD eventually settles to the nominal I.sub.DDQ. This is shown by arrow 125. If the CMOS inverter is defective, the I.sub.DDQ of the device is greater than the nominal value, as shown by arrow 130.
FIG. 2 shows a prior circuit for measuring the quiescent power supply current of a device under test. The circuit 200 is coupled between a power supply 205 of the ATE and the DUT 100. The DUT 100 is shown as including logic 225 coupled in parallel with the inherent capacitance of the DUT 100. The logic 225 includes at least one CMOS inverter as described above.
The circuit 200 includes a switch 210 coupled between the power supply 205 and the DUT, capacitors C1 and C2, and buffer 220. During normal functional testing, the switch 210 is closed, providing a low impedance path between the power supply 205 and the DUT 100. This low impedance path allows the high transient currents that occur when the DUT changes states and provides the power supply voltage V.sub.DD to the DUT 100. The switch 210 is shown as a FET having its gate controlled by a control signal of the ATE.
The circuit 200 measures the amount of quiescent power supply current I.sub.DDQ for the DUT 100 when the switch 210 is opened. To measure the quiescent power supply current I.sub.DDQ, the circuit 200 measures the time rate of change for the voltage at node 215. The input to the buffer 220 provides a high input impedance value such that the only conduction path from the node 215 to system ground VSS is through the DUT 100. The output of the buffer 220, which is equal to the value V.sub.DUT at node 215, is supplied to measurement circuitry in the ATE (not shown).
The circuit operates according to the well-known relationship between current, capacitance, and the time rate of change for voltage, namely: ##EQU1## To measure the quiescent power supply current I.sub.DDQ, the state of the logic 225 is changed in response to an input test vector, giving rise to transient I.sub.DD current. The transient is allowed to subside, and the switch 210 is opened, decoupling the power supply 205 and the capacitor C1 from the node 215. While the switch was closed, the parallel capacitors of C2 and C.sub.DUT were charged the power supply voltage V.sub.DD. When the switch is opened, the parallel capacitors C2 and C.sub.DUT begin to discharge to ground via the DUT 100, giving rise to a current. The amount of current that is conducted via the DUT 100 can be determined using equation 1. To accurately calculate I.sub.DDQ, C.sub.total, which is the parallel capacitance of the capacitors C2 and C.sub.DUT, C.sub.DUT must be known. The requirement that C.sub.DUT must be known is one disadvantage of this prior art I.sub.DDQ measurement technique.
When the switch 210 is opened, the measurement circuitry of the ATE samples and holds the voltage at the output of the buffer 220. After a fixed amount of time equal to .DELTA.t, the voltage at the output of the buffer 220 is sampled again. The difference between the two sampled voltages is determined to yield the change in voltage, .DELTA.V. If the capacitance C.sub.total is known, the quiescent current I.sub.DDQ can be determined using the values .DELTA.t, .DELTA.V, and equation (1), above. The measured I.sub.DDQ value is then compared to an expected I.sub.DDQ value by the ATE, and the result of the comparison indicates whether the DUT passes or fails the I.sub.DDQ measurement test.
FIG. 3 shows the operating characteristics for the circuit of FIG. 2. Prior to time t0, the ATE conducts functional testing of the DUT 100, changing the state of the DUT several times. Curve 305 shows power supply current as a function of time, and curve 310 shows the node voltage V.sub.DUT of node 215 as a function of time. Each current transient is shown as producing a corresponding decrease in the node voltage V.sub.DUT. At time t0, the switch 210 is opened, and the voltage at the output of the buffer 220 is sampled. At time t1, the voltage at the output of the buffer 220 is again sampled. As shown, the node voltage V.sub.DUT decreases over time for both passing and failing devices. The voltage drop for a failing device, however, is much greater than that for a passing device. The precise value of I.sub.DDQ is determined using equation (1), above.
The cycle time for measuring I.sub.DDQ using the circuit 200 is much greater than the cycle time for standard functional testing. The capacitors must be allowed sufficient time to discharge, and the measurement circuitry of the ATE must be allowed sufficient time to detect changes in voltage. Therefore, much of the increase in cycle time is required by the testing mechanism. A significant portion of the increase in cycle time, however, is required by the measurement technique, which requires the quantification of the change in voltage, .DELTA.V.